?20 10 fairchild semiconductor corporation FDG1024NZ rev. c www.fairchildsemi.com 1 FDG1024NZ dual n-channel power trench ? mosfet june 2010 s1 sc70-6 s1 g1 d2 d1 g2 s2 g1 d2 d1 g2 s2 3 2 1 4 5 6 FDG1024NZ dual n-channel powertrench ? mosfet 20 v, 1.2 a, 175 m ? features ? max r ds(on) = 175 m ? at v gs = 4.5 v, i d = 1.2 a ? max r ds(on) = 215 m ? at v gs = 2.5 v, i d = 1.0 a ? max r ds(on) = 270 m ? at v gs = 1.8 v, i d = 0.9 a ? max r ds(on) = 389 m ? at v gs = 1.5 v, i d = 0.8 a ? hbm esd protection level >2 kv (note 3) ? very low level gate drive requirements allowing operation in 1.5 v circuits (v gs(th) < 1 v) ? very small package outline sc70-6 ? rohs compliant general description this dual n-channel logic level enhancement mode field effect transistors are produced using fairchild?s proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance. this device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal mosfets. since bias resistors ar e not required, this dual digital fet can replace several differ ent digital transistors, with different bias resistor values. mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 20 v v gs gate to source voltage 8 v i d -continuous t a = 25c (note 1a) 1.2 a -pulsed 6 p d power dissipation t a = 25c (note 1a) 0.36 w power dissipation t a = 25c (note 1b) 0.30 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 350 c/w r ja thermal resistance, junction to ambient (note 1b) 415 device marking device package reel size tape width quantity .4n f dg1024nz sc70-6 7 ? 8 mm 3000 units
FDG1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 2 ?20 10 fairchild semiconductor corporation FDG1024NZ rev. c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 20 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 14 mv/c i dss zero gate voltage drain current v ds = 16 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 0.4 0.8 1.0 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -3 mv/c r ds(on) static drain to source on resistance v gs = 4.5 v, i d = 1.2 a 160 175 m ? v gs = 2.5 v, i d = 1.0 a 185 215 v gs = 1.8 v, i d = 0.9 a 232 270 v gs = 1.5 v, i d = 0.8 a 321 389 v gs = 4.5 v, i d = 1.2 a, t j =125 c 220 259 g fs forward transconductance v dd = 5 v, i d = 1.2 a 4 s c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1 mhz 115 150 pf c oss output capacitance 25 35 pf c rss reverse transfer capacitance 20 25 pf r g gate resistance 4.6 ? t d(on) turn-on delay time v dd = 10 v, i d = 1.2 a, v gs = 4.5 v, r gen = 6 ? 3.7 10 ns t r rise time 1.7 10 ns t d(off) turn-off delay time 11 19 ns t f fall time 1.5 10 ns q g total gate charge v gs = 4.5 v, v dd = 10 v, i d = 1.2 a 1.8 2.6 nc q gs gate to source charge 0.3 nc q gd gate to drain ?miller? charge 0.4 nc i s maximum continuous drain-source diode forward current 0.3 a v sd source to drain diode forward voltage v gs = 0 v, i s = 0.3 a (note 2) 0.7 1.2 v t rr reverse recovery time i f = 1.2 a, di/dt = 100 a/ s 10 20 ns q rr reverse recovery charge 1.9 10 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. 2. pulse test: pulse width < 30 0 s, duty cycle < 2.0%. 3: the diode connected between the gate and source serves only as protection against esd. no gate overvoltage rating is implied . a. 350 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 415 c/w when mounted on a minimum pad of 2 oz copper.
FDG1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 3 ?20 10 fairchild semiconductor corporation FDG1024NZ rev. c typical characteristics t j = 25 c unless otherwise noted figure 1. 0 0.4 0.8 1.2 1.6 2.0 0 1 2 3 4 5 6 v gs = 1.8 v v gs = 2.5 v pulse duration = 80 s duty cycle = 0.5% max v gs = 3.5 v v gs = 1.5 v v gs = 4.5 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0123456 0.5 1.0 1.5 2.0 2.5 v gs = 2.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 3.5 v v gs = 1.8 v v gs = 1.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 1.2 a v gs = 4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.01.52.02.53.03.54.04.5 0 100 200 300 400 500 600 i d = 1.2 a t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ? ) pulse duration = 80 s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 01234 0 1 2 3 4 5 6 v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c t j = 125 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDG1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 4 ?20 10 fairchild semiconductor corporation FDG1024NZ rev. c figure 7. 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 q g , gate charge (nc) v gs , gate to source voltage (v) i d = 1.2 a v dd = 10 v v dd = 5 v v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 20 5 10 100 300 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100 0.01 0.1 1 10 0.1 ms 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 415 o c/w t a = 25 o c forward bias safe operating area figure 10. 02468101214 10 -3 10 -1 10 10 3 10 5 v gs = 0 v t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) i g , gate leakage current ( a ) gate leakage current vs gate to source voltage figure 11. single pulse maximum power dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 v gs = 4.5 v p ( pk ) , peak transient power (w) t, pulse width (sec) single pulse r ja = 415 o c/w t a = 25 o c typical characteristics t j = 25 c unless otherwise noted
FDG1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 5 ?20 10 fairchild semiconductor corporation FDG1024NZ rev. c figure 12. transient thermal response curve 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.001 0.01 0.1 1 2 single pulse r ja = 415 o c/w duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a typical characteristics t j = 25 c unless otherwise noted
FDG1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 6 ?20 10 fairchild semiconductor corporation FDG1024NZ rev. c dimensional outlin e and pad layout
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mosfet www.fairchildsemi.com ?2010 fairchild semiconductor corporation 7 FDG1024NZ rev. c
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